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AMD EPYC 7773X “Milan-X” Performance & Power Nearly Four Years Later
Nearly four years have passed since AMD launched their EPYC Milan-X processors with 3D V-Cache. When recently rearranging some servers in the lab and realizing the four year anniversary was coming up in March, curiosity got the best of me in wondering where the Linux performance and energy efficiency on Milan-X is now with the latest Linux software stack compared to the numbers when Milan-X launched back in March 2022. ⌘ Read more

Intel Updates Cache Aware Scheduling For Linux With Better NUMA Balancing
Intel engineer Tim Chen has sent out a second version of the proposed Cache Aware Scheduling patches for the Linux kernel to enhance the CPU performance of modern processors sporting multiple cache domains… ⌘ Read more

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Graviton5 Announced With Up To 192 Cores Per Chip, 5x Larger Cache
Amazon AWS today announced Graviton5 as their newest-generation ARM64 server processor for their EC2 cloud. Graviton5 is being promoted as offering 25% higher performance over existing Graviton4 processors… ⌘ Read more

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Google’s Vibe Coding Platform Deletes Entire Drive
A Google Antigravity user says the AI-driven “vibe coding” tool accidentally wiped his entire D: drive while trying to clear a project cache. Google says it’s investigating, but the episode adds to a growing list of AI tools behaving in ways that “would get a junior developer fired,” suggests The Register. From the report: We reached out to the user, a photographer and g … ⌘ Read more

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HQspinlock Proposal For Linux Shows Very Nice Performance Benefits For Large Servers
A Huawei engineer has sent out patches proposing HQspinlock as a Hierarchical Queued NUMA-aware spinlock for the Linux kernel. HQspinlock aims to addresss inefficiencies within the Linux kernel’s spinlock on modern NUMA-systems due to frequent and costly cross-NUMA cache-line transfers… ⌘ Read more

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HiSilicon Proposes “Cache Lockdown” Driver For More Control Over L3 Cache
A Huawei engineer sent out a proposed driver for the Linux kernel to enable “cache lockdwon” behavior for HiSilicon ARM64 processors for greater control over the processor’s L3 cache usage… ⌘ Read more

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Intel Working On Linux Support For New Power Savings Feature With Xe3P_LPD
The upcoming Linux 6.19 kernel cycle is set to introduce initial support for Xe3P graphics to be found initially with Nova Lake processors. While that initial support is landing for Linux 6.19, other extra Xe3P features are still to be added to the open-source kernel driver over coming release cycles. One of those extra features being currently tackled is a new element with Xe3P_LPD: the ability to use the system cache for FBC… ⌘ Read more

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Tokyo Court Finds Cloudflare Liable For Manga Piracy in Long-Running Lawsuit
A Tokyo court ruled that Cloudflare is liable for aiding manga piracy after failing to act on infringement notices and continuing to cache and serve content for major piracy sites, awarding about $3.2 million in damages. TorrentFreak says the decision sets a significant precedent in Japan, suggesting CDN providers can face … ⌘ Read more

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@prologic@twtxt.net Hm, same startup delay. (Go is not an option for me anyway.)

It’s hard to tell why all this is so slow. Maybe in this particular case it has something to do with fonts: strace shows the program loading the fontconfig configs several times, and that takes up a bulk of the startup time. 🤔 (Qt6 or Java don’t do that, but they’re still slow to start up – for other reasons, apparently.)

To be fair, it’s “just” the initial program startup (with warm I/O caches). Once it’s running, it’s fine. All toolkits I’ve tried are. But I don’t want to accept such delays, not in the year 2025. 😅 Imagine every terminal window needing half a second to appear on the screen … nah, man.

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Mysterious animal bones found at site of Edinburgh hillside wildfire
Rangers have discovered a cache of unusual animal bones high up on the hillside near Arthur’s Seat in Edinburgh. When the historic hillside went up in… ⌘ Read more

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Auto cleanup weak pointer caches
1 points posted by johnsiilver ⌘ Read more

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Cache-Friendly, Low-Memory Lanczos Algorithm in Rust
Comments ⌘ Read more

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Ironclad 0.7.0 and 0.8.0 released, adds RISC-V support
We’ve talked about Ironclad a few times, but there’s been two new releases since the 0.6.0 release we covered last, so let’s see what the project’s been up to. As a refresher, Ironclad is a formally verified, hard real-time capable kernel written in SPARK and Ada. Versions 0.7.0 and 0.8.0 improved support for block device caching, added a basic NVMe driver, added support for x86’s SMAP, switched from KVM to NVMM for Ironcla … ⌘ Read more

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@eldersnake@we.loveprivacy.club What version are you running btw? It’s probably time you upgraded and time I released a new version finally 😂 If you’re running a version that’s pre-SQLite-cache, then yeah I’m not surprised. The SQLite cache version is honestly much better 🤣

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Intel ANV Vulkan Driver Finally Exposes Pipeline Binary “VK_KHR_pipeline_binary”
Introduced back in August of 2024 with Vulkan 1.3.294 was VK_KHR_pipeline_binary as a pipeline binary extension to retrieve binary data associated with individual pipelines. The focus of this is to bypass the Vulkan pipeline caching mechanism and so applications can manage caches themselves. Finally today for Mesa 26.0-devel the Intel “ANV” open-source Vulkan driver has enabled this extension… ⌘ Read more

When I realize my issue was just a caching problem ⌘ Read more

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